1. Field of the Invention
The present invention relates generally to computers. More specifically, the present invention relates to the automatic accumulation of ports of a switch.
2. Description of the Related Art
There are many different computer Input/Output (I/O) interconnect standards available. One of the most popular over the years has been the Peripheral Component Interconnect (PCI) standard. PCI allows a bus to act like a bridge, which isolates a local processor bus from the peripherals, allowing a Central Processing Unit (CPU) of the computer to run must faster.
Recently, a successor to PCI has been popularized. Termed PCI Express (or, simply, PCIe), PCIe provides higher performance, increased flexibility and scalability for next-generation systems, while maintaining software compatibility with existing PCI applications. Compared to legacy PCI, the PCI Express protocol is considerably more complex, with three layers—the transaction, data link and physical layers.
In a PCI Express system, a root complex device connects the processor and memory subsystem to the PCI Express midpoint device fabric comprised of zero or more midpoint devices. These midpoint devices are commonly referred to as “switches”, although they can include functionality not found in traditional switches. Nevertheless, the term “switches” as used throughout this disclosure shall be interpreted broadly to mean any midpoint device that handles communications among multiple ports.
In PCI Express, a point-to-point architecture is used. Similar to a host bridge in a PCI system, the root complex generates transaction requests on behalf of the processor, which is interconnected through a local I/O interconnect. Root complex functionality may be implemented as a discrete device, or may be integrated with the processor. A root complex may contain more than one PCI Express port and multiple midpoint devices can be connected to ports on the root complex or cascaded.
When initializing a link at the physical layer of one of the ports of a PCI Express switch, a Link Training & Status State Machine (LTSSM) is utilized. The LTSSM essentially acts as a physical layer controller. It establishes each link between the PCI Express switch and another device. Part of this involves determining how wide each link is going to be. How wide a link can be depends on the number of lanes the switch has available as well as the number of lanes the link partner (the device to which the switch is attempting to connect) has available.
FIG. 1 is a diagram illustrating the states of a traditional LTSSM. Prior to entering these states, the switch will determine how many links to attempt to establish. Then, for each link to attempt to establish, a link request will be sent out on all available lanes. The link partners respond to these link requests by sending back information on how many lanes are available on the link partner side. When the first such response is received by the switch, the switch starts an LTSSM for that particular link. A detect state 100 is used to detect when a far end termination is present. Then a polling state 102 transmits training ordered sets and responds to training ordered sets that are received. In this state, bit lock and symbol lock are established, lane polarity is configured, and lane data rate is established. The polling state 102 also includes a polling compliance sub-state, that is used to determine if the transmitter and the interconnect is compliant with voltage and timing specifications.
In a configuration state 104, both the transmitter and receiver are sending and receiving data at the negotiated data rate. The lanes of a port are configured into a link through a width and lane negotiation sequence. Additional configuration details can be configured during this state. Once this is completed, the state machine can progress to L0 106, which is the normal operating state where data and control packets can be transmitted and received. Various power management states can be entered from this state, including L0s 108, L1 110, and L2 112. Additional available states include recovery 114 (where a link can re-establish bit lock, symbol lock, and lane-to-lane de-skew), disabled 116 (where a link is disabled), loopback 118 (used for test and fault isolation), and hot reset 120 (used to reset the state machine).
Following the configuration state 104, the switch then will start an LTSSM for one of the remaining links to establish (if any). That LTSSM then proceeds through all of its states until the configuration state is completed, at which point the switch then proceeds to start another LTSSM for another of the remaining links to establish. This process repeats until all links have been established.
While this kind of state machine operates effectively in prior art devices, it does not operate all that efficiently when configuring multiple ports simultaneously. Specifically, configuring multiple ports currently requires running through the state machine for each port, waiting until the last port is completely configured (entered state L0) before proceeding to the next port. Thus, for an 8 port configuration, the system must run through the state machines for all 8 ports before configuration is done. Even if all these state machines require the same time to configure, it still results in taking eight times as long as configuring a single port. Additionally, in real world environments, some state machines can take significantly longer to configure than others, which can slow down the entire process and delay proceeding to the next port configuration.
What is needed is a solution that does not suffer from these issues.